SFMSHD=0, SFMSLD=0, SFMSW=0x0
Chip Selection Control Register
SFMSW | Minimum High-level Width Select for QSSL Signal 0 (0x0): 1 QSPCLK 1 (0x1): 2 QSPCLK 2 (0x2): 3 QSPCLK 3 (0x3): 4 QSPCLK 4 (0x4): 5 QSPCLK 5 (0x5): 6 QSPCLK 6 (0x6): 7 QSPCLK 7 (0x7): 8 QSPCLK 8 (0x8): 9 QSPCLK 9 (0x9): 10 QSPCLK 10 (0xA): 11 QSPCLK 11 (0xB): 12 QSPCLK 12 (0xC): 13 QSPCLK 13 (0xD): 14 QSPCLK 14 (0xE): 15 QSPCLK 15 (0xF): 16 QSPCLK |
SFMSHD | QSSL Signal Hold Time 0 (0): QSSL outputs high after 0.5 QSPCLK cycles from the last rising edge of QSPCLK. 1 (1): QSSL outputs high after 1.5 QSPCLK cycles from the last rising edge of QSPCLK. |
SFMSLD | QSSL Signal Setup Time 0 (0): QSSL outputs low before 0.5 QSPCLK cycles from the first rising edge of QSPCLK. 1 (1): QSSL outputs low before 1.5 QSPCLK cycles from the first rising edge of QSPCLK. |